In computer systems having multiple central processing units (CPUs) that operate faster than the main memory they use, providing separate memory for each processor can alleviate the reduction in performance that occurs when several processors attempt to address the same memory. When more than one processor requires the data stored on a memory, including additional hardware to move data between memory banks slows the processors attached to those banks. In response to such issues, non-uniform memory access (NUMA) computer architectures have been developed to provide high-bandwidth, memory-coherent connectivity between processors in multi-processor systems.
High performance processors designed for such multi-processor systems can support a memory-coherent packet interface between a small number of processor sockets, by which messages can be transferred between sockets via high-speed intersocket links known as processor interconnects. The resulting group of interconnected processor sockets is often referred to as a node or clump. This processor packet interface may also support node controllers used to coherently interconnect a number of processor nodes into a larger shared-memory multi-processor system. The processor sockets have a limited number of socket identifiers, such that from a given processor socket's perspective, there are a limited number of other sockets visible. A node controller may proxy many remote nodes or sockets as one socket with a very large memory using secondary interconnect network that is lower bandwidth than processor interconnects within each node.